Building the ZPUino

Posted by: Dave Vandenbout 6 years ago

(2 comments)

In my last post, I introduced Alvaro Lopes' ZPUino port for the XuLA2. As I pointed out, the bitstream file he provides only works on the XuLA2-LX9, so now I'll show you how to rebuild the ZPUino from source.

First, you'll need the VHDL source for the ZPUino. If you already have git installed, then you can clone it directly like this:

git clone https://github.com/alvieboy/ZPUino-HDL.git my_zpuino_hdl

If you don't have git installed and don't want to, then you can just download a zip file with everything in it and unpack it somewhere.

Once the ZPUino source files are installed, go to one of the following directories and open a terminal or command window:

• my_zpuino_hdl/zpu/hdl/zpuino/boards/xula2/S6LX9 if you have a XuLA2-LX9 board.
• my_zpuino_hdl/zpu/hdl/zpuino/boards/xula2/S6LX25 if you have a XuLA2-LX25 board.

There are only a few files in the directory, but the most important one (for right now) is Makefile. Instead of using the Xilinx ISE GUI tool, Alvie drives his FPGA compilation using make (which I've also talked about). This is great because all you have to do is call make and the ZPUino bitstream will pop out a few minutes later. But before you can do that, you'll need to make sure your environment is set up correctly like so:

1. Install a version of the Xilinx ISE tools. Although the GUI isn't used, we'll still need Xilinx's command-line programs to synthesize/map/place/route the ZPUino VHDL into the FPGA.

2. Install the ZPUino IDE as I discussed in my last post. We'll need it's C/C++ compiler to build the bootloader that's embedded into the ZPUino bitstream.

3. Within the ZPUino IDE directory, open the zpuino-2.0.0/hardware/zpuino/zpu20/boards.txt file and add the descriptions for the XuLA2-LX9 and -LX25 boards by replacing:

   zpuino20_xula2_lx9.name=ZPUino 2.0 on XuLA2 (LX9)
   zpuino20_xula2_lx9.boardid=0xB6011900
   zpuino20_xula2_lx9.upload.protocol=zpuino-serial
   zpuino20_xula2_lx9.upload.maximum_size=8388608
   zpuino20_xula2_lx9.upload.size_sections=all
   zpuino20_xula2_lx9.upload.speed=1000000
   zpuino20_xula2_lx9.upload.tool=zpuinoprogrammer
   zpuino20_xula2_lx9.build.f_cpu=96000000L
   zpuino20_xula2_lx9.build.core=zpuino
   zpuino20_xula2_lx9.build.mcu=zpu
   zpuino20_xula2_lx9.build.toolchain=zpu
   zpuino20_xula2_lx9.build.board=ZPUINO_XULA2
   zpuino20_xula2_lx9.build.extra_flags=-D__ZPUINO_XULA2__ -DBOARD_ID=0xB6011900 -DBOARD_MEMORYSIZE=0x2000000 -nostartfiles
   zpuino20_xula2_lx9.build.extraSflags=-DBOARD_ID=0xB6011900
   

   with:

   zpuino20_xula2_lx9.name=ZPUino 2.0 on XuLA2 (LX9)
   zpuino20_xula2_lx9.boardid=0xB6011900
   zpuino20_xula2_lx9.upload.protocol=zpuino-serial
   zpuino20_xula2_lx9.upload.maximum_size=8388608
   zpuino20_xula2_lx9.upload.size_sections=all
   zpuino20_xula2_lx9.upload.speed=1000000
   zpuino20_xula2_lx9.upload.tool=zpuinoprogrammer
   zpuino20_xula2_lx9.build.f_cpu=96000000L
   zpuino20_xula2_lx9.build.core=zpuino
   zpuino20_xula2_lx9.build.mcu=zpu
   zpuino20_xula2_lx9.build.toolchain=zpu
   zpuino20_xula2_lx9.build.board=ZPUINO_XULA2
   zpuino20_xula2_lx9.build.extra_flags=-D__ZPUINO_XULA2__ -DBOARD_ID=0xB6011900 -DBOARD_MEMORYSIZE=0x2000000 -nostartfiles
   zpuino20_xula2_lx9.build.extraSflags=-DBOARD_ID=0xB6011900
   ##############################################################
   zpuino20_xula2_lx25.name=ZPUino 2.0 on XuLA2 (LX25)
   zpuino20_xula2_lx25.boardid=0xBA011900
   zpuino20_xula2_lx25.upload.protocol=zpuino-serial
   zpuino20_xula2_lx25.upload.maximum_size=8388608
   zpuino20_xula2_lx25.upload.size_sections=all
   zpuino20_xula2_lx25.upload.speed=1000000
   zpuino20_xula2_lx25.upload.tool=zpuinoprogrammer
   zpuino20_xula2_lx25.build.f_cpu=96000000L
   zpuino20_xula2_lx25.build.core=zpuino
   zpuino20_xula2_lx25.build.mcu=zpu
   zpuino20_xula2_lx25.build.toolchain=zpu
   zpuino20_xula2_lx25.build.board=ZPUINO_XULA2
   zpuino20_xula2_lx25.build.extra_flags=-D__ZPUINO_XULA2__ -DBOARD_ID=0xBA011900 -DBOARD_MEMORYSIZE=0x2000000 -nostartfiles
   zpuino20_xula2_lx25.build.extraSflags=-DBOARD_ID=0xBA011900
   

4. Also in the ZPUino IDE directory, open the zpuino-2.0.0\hardware\zpuino\zpu20\cores\zpuino\board_xula2.h file and replace:

   #define SPIOFFSET 0x60000
   

   with:

   #define SPIOFFSET 0xD0000
   

5. Install a perl interpreter. If this is too much for you, later I'll show you how to modify the makefile to avoid it.

Once you've got these things installed, under linux you're probably good to go and can just type make and the ZPUino bitstream file will appear in a couple of minutes. But for Windows, I like to create a setenv.bat file that has the following commands in it (you'll have to modify this script depending upon where you've installed your tools):

REM Delete any existing path to executables.
set path=

REM Add the path to the Xilinx command-line tools.
call C:\Xilinx_ISE\14.7\ISE_DS\settings64.bat

REM Add the path to the ZPUino compiler/linker/assembler.
set path=C:\TEMP\zpuino-2.0.0\hardware\tools\zpu\bin;%path%
set path=C:\TEMP\zpuino-2.0.0\hardware\tools\zpu\zpu-elf\bin;%path%

REM Append the path to the perl interpreter.
set path=%path%;C:\perl\bin

Then I just issue the following commands in the command window:

> setenv.bat
> make

After all this, you should be rewarded with a bright, shiny, new xula2_routed.bit file that you can download into your XuLA2 board and talk to with the IDE as I described in my previous post.

One side-effect of compiling the ZPUino is that now we can see how much of the FPGA is free for other logic. I extracted the following information from the xula2.mrp file for the LX9 and LX25 FPGA compilations:

So over half of the FPGA is still empty in the smaller LX9 FPGA, and over 80% is free in the larger LX25. What can we do with all that unused logic? I'll talk about that in a later post.

FAQ for Windows Users

If you're trying to recompile the ZPUino using the makefile on Windows, you might run into some problems. Here are some solutions for the ones I encountered.

The makefile aborts when it tries to make the xst\projnav.tmp directory.

Open the makefile and replace mkdir with gmkdir.

The makefile aborts because I don't have a perl interpreter.

You can always install a perl interpreter, but the Xilinx ISE software already has one called xilperl. To use that one, open my_zpuino_hdl/zpu/hdl/zpuino/bootloader/Makefile and change perl to xilperl on lines 44 and 45.

At the end of the compilation, I get an error dialog that says "wbtc.exe has stopped working".

This happens when the ISE software tries to use WebTalk to send usage stats to Xilinx. To stop it, in the ISE Project Navigator click on Edit => Preferences and then click on the WebTalk category. Uncheck the Enable WebTalk box. However, you don't really need to worry about this error. As long as you have the xula2_routed.bit file, you're golden.

I'm getting an error: zpu-elf-g++: Command not found

This happens when the makefile can't find the ZPUino compiler tools that were installed as part of the ZPUino IDE. One way to avoid this error is to edit the makefile to remove the command to build the bootloader.vhd file and just use the one that's already included for the XuLA2 ZPUino.

Or you can modify your OS search path to find the ZPUino tools. On Windows, I use the following command file to do this:

REM Setup the path environment variable so the makefile will work. You will have to change this for your particular operating environment.

REM Delete any existing path to executables.
set path=

REM Add the path to the Xilinx command-line tools.
call C:\Xilinx_ISE\14.7\ISE_DS\settings64.bat

REM Add the path to the ZPUino compiler/linker,assembler.
set path=C:\TEMP\zpuino-2.0.0\hardware\tools\zpu\bin;%path%
set path=C:\TEMP\zpuino-2.0.0\hardware\tools\zpu\zpu-elf\bin;%path%

REM Append the path to the perl interpreter.
set path=%path%;C:\perl\bin

You'll have to modify the paths to match what's used on your system, but you get the idea.

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