Description

Dualport Module for the SDRAM Controller

• Dualport Module for the SDRAM Controller
• DESIGN FILES
• USING THE DESIGN EXAMPLE
• ENVIRONMENT
• SOURCE FILES
• AUTHOR
• COPYRIGHT AND LICENSE
• HISTORY

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Dualport Module for the SDRAM Controller

This application note describes a module that adds dualport read/write access to the host-side port of the XESS SDRAM controller.

The dualport module attaches to the host-side port of the XESS SDRAM controller and splits it into two identical host-side ports. Each of these ports operates identically to the orignal host-side port so no modifications are needed in any applications that used the original SDRAM controller. An application performs memory read/write operations on its port independently of any operations that occur on the other port. The total SDRAM bandwidth can be allocated between the two ports to match the data rates of the attached applications. Dualport modules can be cascaded to build SDRAM interfaces with three or more independent ports.

An example with two independent modules that each write random data to separate sections of the SDRAM and then verify it is provided to show how the dualport module is used.

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DESIGN FILES

• common.vhd
This file contains some definitions and functions used in the rest of the VHDL code.

• memtest.vhd, randgen.vhd
These VHDL files describe a memory tester module that writes a stream of data from a random-number generator (RNG) to a storage device and then reads the data back and compares it to the RNG output to verify it was stored correctly.

• sdramcntl.vhd
This file describes the SDRAM controller and the associated dualport module. You can read a more detailed explanation of the dualport module at /appnotes/an-071205-dualport.pdf. You can read a more detailed explanation of the SDRAM controller at /appnotes/an-071205-xsasdramcntl.pdf.

• xsasdramcntl.vhd
This VHDL file surrounds the generic SDRAM controller with a wrapper that customizes it for the XSA Boards.

• test_dualport_core.vhd
This file combines two memory testers, the dualport module and the SDRAM controller core to make the complete SDRAM tester.

• test_dualport.vhd
This file instantiates the test_dualport_core module to create a dualport SDRAM tester for a particular board.

• test_dualport.ucf
This file contains the pin assignments for the I/O signals of the dualport SDRAM tester for a particular board.

• test_board.npl
Open this project file with WebPACK if you need to recompile the design.

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USING THE DESIGN EXAMPLE

• Step 1:
Attach a DC power supply to the XSA Board.

• Step 2:
Attach the downloading cable from the PC parallel port to the XSA Board.

• Step 3:
Set jumper J9 on the XSA Board to XS.

• Step 4:
Download the default parallel port interface into the XSA-3S1000 (\XSTOOLS\XSA\3S1000\dwnldpar.svf) if it is not already present. (Running GXSTEST will do this automatically.)

• Step 5:
Download the

test_dualport.bit

file to the XSA Board.

• Step 6:
Once the test_dualport.bit file is downloaded into the XSA Board, you should see the status of the upper and lower SDRAM tests reflected in the activation of the LED segments. The LED segments are labeled as follows:

             S6
            +====+
          S5| S3 |S4
            |====|
          S2|    |S1
            +====+
              S0

The meaning of the LED segment activations is as follows:

       Lower Memory Status            S0    S1    S2
        ===============================================
        Initialization                 ON    OFF   OFF
        -----------------------------------------------
        Writing RNG sequence to the    OFF   ON    OFF
        lower half of SDRAM

        -----------------------------------------------
        Reading data from the lower    OFF   OFF   ON
        half of the SDRAM and
        comparing it to RNG sequence
        -----------------------------------------------
        Passed - no mismatches found   OFF   OFF   OFF
        -----------------------------------------------
        Failed - mismatches found      ON    ON    ON
        -----------------------------------------------

       Upper Memory Status            S3    S4    S5
        ===============================================
        Initialization                 ON    OFF   OFF
        -----------------------------------------------
        Writing RNG sequence to the    OFF   ON    OFF
        upper half of SDRAM

        -----------------------------------------------
        Reading data from the upper    OFF   OFF   ON
        half of the SDRAM and
        comparing it to RNG sequence
        -----------------------------------------------
        Passed - no mismatches found   OFF   OFF   OFF
        -----------------------------------------------
        Failed - mismatches found      ON    ON    ON
        -----------------------------------------------

The memory test will run repeatedly as long as pushbutton SW2 on the XSA Board is pressed. You should see that the S4-S5 LEDs flash more quickly than the S1-S2 LEDs. Because port 1 is allocated more time slots than port 0, the upper half of memory can be tested in less time so the associated LEDs flash more quickly than those for the lower half.

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ENVIRONMENT

This example design was developed using the following version of software:

      Xilinx WebPACK       : 6.3.03i

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SOURCE FILES

You can download the source files for this example design from the XESS website at /projects/dualporttst-1_1.zip .

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AUTHOR

Dave Vanden Bout, X Engineering Software Systems Corp.

Send bug reports to bugs@xess.com.

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COPYRIGHT AND LICENSE

Copyright 2006 by X Engineering Software Systems Corporation.

This application can be freely distributed and modified as long as you do not remove the attributions to the author or his employer.

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HISTORY

04/06/2006 - Initial release.