| TEST_LCD Project Status | |||
| Project File: | Test_LCD.ise | Current State: | Programming File Generated |
| Module Name: | LCD_Controller |
|
No Errors |
| Target Device: | xc2s200-5fg256 |
|
No Warnings |
| Product Version: | ISE, 8.1i |
|
Sat Aug 4 17:42:50 2007 |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 94 | 4,704 | 1% | |
| Number of 4 input LUTs | 91 | 4,704 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 87 | 2,352 | 3% | |
| Number of Slices containing only related logic | 87 | 87 | 100% | |
| Number of Slices containing unrelated logic | 0 | 87 | 0% | |
| Total Number 4 input LUTs | 157 | 4,704 | 3% | |
| Number used as logic | 91 | |||
| Number used as a route-thru | 66 | |||
| Number of bonded IOBs | 11 | 176 | 6% | |
| Number of GCLKs | 1 | 4 | 25% | |
| Number of GCLKIOBs | 1 | 4 | 25% | |
| Total equivalent gate count for design | 1,709 | |||
| Additional JTAG gate count for IOBs | 576 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Sat Aug 4 17:41:41 2007 | 0 | 0 | 0 |
| Translation Report | Current | Sat Aug 4 17:41:59 2007 | 0 | 0 | 0 |
| Map Report | Current | Sat Aug 4 17:42:05 2007 | 0 | 0 | 2 Infos |
| Place and Route Report | Current | Sat Aug 4 17:42:15 2007 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | Sat Aug 4 17:42:19 2007 | 0 | 0 | 2 Infos |
| Bitgen Report | Current | Sat Aug 4 17:42:50 2007 | 0 | 0 | 0 |